1. Field of the Invention
This invention relates generally to modems, and more specifically to a timing network responsive to equalization multiplying coefficients to recover and control the timing of an automatic digital modem.
2. Description of the Prior Art
With the advent of large scale data processing systems, it has become increasingly desirable to transmit digital data over long distances with a high degree of accuracy. For example, a chain of retail stores might have a central warehouse facility with which each of the stores might advantageously communicate to maintain its respective inventory. A branch bank might also find it desirable to transmit accounting data to a central accounting facility.
Digital modems for transmitting data between first and second data processing apparatuses have included transmitter means for encoding the data received from the first data processing apparatus. An analog signal has been modulated in accordance with the encoded data for transmission typically on a telephone line. At a distant location, a receiver has demodulated the analog signal and decoded the data for introduction to the second data processing apparatus.
In the receiver, the analog signal has been introduced to an analog-to-digital converter or sampler wherein the signal has been sampled at a particular rate and in accordance with variable timing. Sampled values have been coherently demodulated to provide a stream of digital symbols in each of an in-phase channel and a quadrature channel. These channels have each included a lowpass filter providing the receiver with a desired passband. From the lowpass filters, the data symbols have been introduced to an equalization network for correcting any interchannel and intersymbol interference caused by delay and attenuation distortion of the signals resulting from transmission. Following equalization, the signals in the in-phase and quadrature channels have been decoded for introduction to the second data processing apparatus.
Signals at the outputs of the lowpass filters in the in-phase and quadrature channels have expressed positive and negative integer values which have been related to the data. Since the symbols have expressed integer values on opposite sides of a zero level, an eye pattern has been formed with a plurality of level crossings. It has been desirable to time the sampler so that samples are taken at times corresponding to the level crossings. This has provided for detection of symbol levels at a time when the symbols are relatively distinct.
To provide timing for the sampler, a signal has been derived from the eye pattern following the lowpass filter in one of the in-phase and quadrature channels. This signal has provided changes in magnitude at each of the level crossings and these changes have been correlated with the pulses of the modem clock to advance or retard the modem clock and hence the sampling of the sampler.
This timing system has not been particularly effective since the eye pattern at the output of the lowpass filters has been substantially closed by noise related to intersymbol and interchannel interference. As noted, the correction of this type of interference has been accomplished subsequently by the equalization network. Also, the slope of the eye pattern signal at the level crossing has not been particularly great. As a consequence, the magnitude of the timing error signal has not varied substantially with the magnitude of the timing error. Furthermore, considerable circuitry has been used to implement this timing technique. Complex timing algorithms for detecting not only the magnitude but also the slope of the eye pattern signal has relied upon elaborate circuitry to control the timing.
In accordance with the timing techniques of the prior art, a significant number of samples, such as eight, have been used to accurately determine the level crossings of the recovered data signal and hence the timing error. Since only one sample per symbol is needed for normal modem operation, the processing of eight samples per symbol has extended the time necessary to process the demodulated signal and has resulted in a significant increase in the complexity of the implementation circuitry.
Following the lowpass filters, the signals in each of the in-phase and quadrature channels have been introduced to an equalization network. The equalization has included a plurality of multipliers and a plurality of registers each including a plurality of taps. As the symbols have been sequentially introduced to the multipliers, the taps have provided a variable multiplying coefficient to each of the multipliers. The resulting products have been summed to correct for the interchannel and intersymbol interference in the symbols.
These digital modems have also included a phase correction network. This network has corrected for phase and frequency offset as well as phase jitter.
In these digital modems of the prior art, the timing, phase correction, and equalization have each been updated in accordance with error signals which have been independently derived. It is, of course, desirable that all of these functions be updated in accordance with a single error signal in order to minimize the cost and complexity of implementation.